1. Field of the Invention
The present invention relates to a storage device and a semiconductor device. More specifically, the present invention relates to a storage device composed of memory cells each using a storage element storing and holding information according to an electric resistance state and a semiconductor device having this storage device.
2. Description of Related Art
In information equipment such as a computer, high density DRAM (Dynamic Random Access Memory) with high operation speed is widely used as a random access memory.
However, since DRAM is volatile memory, which loses information upon turning off power, nonvolatile memory, which holds information after turning off power, has been desired.
As nonvolatile memory which is considered to be promising, there are proposed FeRAM (Ferroelectric Random Access Memory), MRAM (Magnetoresistive Random Access Memory), phase change memory, and resistance change type memory such as PMC (Programmable Metallization Cell) and RRAM.
The above-mentioned memories can hold written information for a long time without supplying power. Furthermore, it is considered that in the case of the above-mentioned memories, their non-volatility can make refreshing operation unnecessary and reduce power consumption.
Moreover, the resistance change type nonvolatile memory such as PMC and RRAM has a comparatively simple constitution in which a material having a property that a resistance value is changed by applying a voltage or a current is used for a storage layer storing and holding information, and two electrodes are provided so as to sandwich the storage layer therebetween and a voltage or a current are applied to these two electrodes. Therefore, the miniaturization of the storage element is easily achieved.
PMC has a structure in which an ionic conductor containing a predetermined metal is sandwiched between the two electrodes, and further, PMC utilizes a property that when causing the metal contained in the ionic conductor to be contained in either of the two electrodes and applying a voltage between the two electrodes, electric properties of the ionic conductor such as resistance or capacitance are changed.
More specifically, the ionic conductor is composed of a solid solution of chalcogenide and the metal (for example, amorphous GeS or amorphous GeSe), and either of the two electrodes contains Ag, Cu or Zn (for example, refer to Patent Document 1).
As a constitution of RRAM, there is introduced a constitution, for example, in which a polycrystalline PrCaMnO3 thin film is sandwiched between two electrodes and by applying voltage pulses or current pulses, a resistance value of the PrCaMnO3 which is a recording film is largely changed (for example, refer to Non-Patent Document 1). In addition, at information recording (writing) time and erasing time, voltage pulses different in polarity are applied.
Furthermore, as another constitution of RRAM, there is introduced a constitution, for example, in which SrZrO3 (monocrystal or polycrystal) with a small quantity of Cr doped is sandwiched between two electrodes, and by causing current to flow from these electrodes, the resistance of a recording film is changed (for example, refer to Non-Patent Document 2).
In this Non-Patent Document 2, I-V characteristics of the storage layer are shown and threshold voltages in recording and erasing are ±5 V. In this constitution, the application of voltage pulses also enables recording and erasing. A necessary pulse voltage is ±1.1 V and a voltage pulse width is 2 ms. Furthermore, high speed recording and erasing is enabled and the operation at a voltage pulse width of 100 ns is reported. In this case, a necessary pulse voltage is ±5 V.
However, at present, it is difficult for FeRAM to perform nondestructive reading and since it performs destructive reading, the reading speed is slow. Furthermore, polarization reversal according to reading or recording is limited in number of times, thereby limiting writing in number of times.
Furthermore, since MRAM needs a magnetic field for recording, and a current flowing through wiring generates the magnetic field, a large amount of current is necessary in recording.
Furthermore, the phase change memory is memory in which voltage pulses with the same polarity and different magnitudes are applied to perform recording. Since this phase change memory performs switching by using temperature, there is an issue that it is sensitive to changes in environmental temperature.
Furthermore, PMC described in Patent Document 1, a crystallization temperature of amorphous GeS or amorphous GeSe is about 200° C., and crystallization of the ionic conductor deteriorates the properties. Accordingly, PMC disadvantageously cannot endure high temperatures in a step of manufacturing a storage element, for example, in a step of forming a CVD insulating film, a protecting film or the like.
Moreover, since both of the materials of the storage layers proposed in the constitutions of RRAM's described in Non-Patent Document 1 and Non-Patent Document 2 are crystalline, RRAM has problems that thermal processing at about 600° C. is necessary, that it is extremely difficult to manufacture monocrystal of the proposed materials, that miniaturization is difficult because the use of polycrystal brings about the influence of grain boundary, etc.
Furthermore, in the above-described RRAM's, it is proposed that a pulse voltage is applied for recording and erasing of information. However, in the proposed constitutions, the resistance value of the storage layer is changed after recording, depending on the pulse width of the applied pulse voltage. Such dependency of the resistance value after recording on the pulse width of the recording indirectly means that the resistance value is changed even if the same pulse is repeatedly applied.
For example, in the above-described Non-Patent Document 1, it is reported that in the case where the pulses with the same polarity are applied, the resistance value after recording is largely changed, depending on the pulse width. The resistance value has a characteristic that in the case of a short pulse width of not more than 50 ns, a resistance change rate by recording is smaller, and that in the case of a long pulse width of not less than 50 ns, as the pulse width becomes longer, the resistance value conversely approximates a resistance value before recording instead of being saturated at a certain value. Furthermore, Non-Patent Document 1 introduces features of a memory structure in which a storage layer and a MOS transistor for access control are connected in series, and arranged in an array. Here, it is reported that when the pulse width is changed within a range of 10 ns to 100 ns, the resistance value of the storage layer after recording is changed according to the pulse width. In the case of a still longer pulse width, the resistance is predicted to decrease again due to the property of the storage layer.
Namely, in RRAM, since the resistance value after recording depends on the magnitude of the pulse voltage and the pulse width, fluctuations in the magnitude of the pulse voltage and the pulse width cause fluctuations in the resistance value after recording.
Accordingly, a pulse voltage with a pulse width shorter than about 100 ns has a small resistance change rate by recording and easily comes under the influence of the fluctuations in the resistance value after recording. Therefore, it is difficult to perform stable recording.
Consequently, when recording at such a short-pulse voltage, a process (verification) of checking contents of information after recording needs to be performed in order to ensure recording.
For example, before recording, a process of reading and checking contents of information recorded on a storage element (resistance values of the storage layer), and recording is performed corresponding to a relationship between the checked contents (resistance values) and contents to be recorded (resistance values). Alternatively, for example, after recording, a process of reading and checking contents of information recorded on the storage element, and when the checked resistance is different from a desired resistance value, re-recording is performed to correct the resistance value to the desired one.
The above-described processes makes the time required for recording longer, and thus makes it difficult to overwrite data or the like at high speed.
In order to solve the above-described problems, there is proposed a storage device including a memory cell having a storage element having a characteristic that the application of a voltage not lower than a threshold voltage between both terminals changes a resistance value, and a circuit element connected to the storage element in series, which is a load, and the storage device has a characteristic that when the voltage applied between respective terminals of the storage element and the circuit element is not lower than a certain voltage which is higher than the threshold voltage, a combined resistance value of the storage element and the circuit element of the memory cell after the resistance value of the storage element has been changed from a high resistance value state to a low resistance value state becomes an almost steady value regardless of the magnitude of the voltage (refer to Patent Document 2). This storage device realizes stable recording and shortens the time required for recording of information.
[Patent Document 1] National Publication of Japanese Patent Application Translation No. 2002-536840
[Non-Patent Document 1] “Novel Colossal Magnetoresistive Thin Film Nonvolatile Resistance Random Access Memory (RRAM)” by W. W. Zhuang et al., Technical Digest “International Electron Devices Meeting”, 2002, pp. 193
[Non-Patent Document 2] “Reproducible switching effect in thin oxide films for memory applications”, by A. Beck et al., Applied Physics Letters, 2000, Vol. 77, pp. 139–141,
[Patent Document 2] Specification of Japanese Patent Application No. 2004–22121